Extended 90 nm CMOS Technology with High Manufacturability for High-Performance, Low-Power, RF/Analog Applications

High-density, 90 nm CMOS technology has been suggested for generic, low-voltage, high-performance applications. In this paper, we describe some strategies for extending the previous technology in order to fabricate the following: 1) a low-standby-power transistor with high drivability for low-power applications, 2) a high-drivability transistor, inductor, and MIM capacitor for RF/analog applications, 3) up to 10 layers of high-reliability, dual damascene Cu/very-low-k (VLK) and Al interconnects. Our low-standby-power, 90 nm transistor consumes only 10% of the standby power consumed by 130 nm transistors, and this is achieved with no degradation of circuit speed. Using 90 nm technology, we have fabricated up to 10 layers of interconnects and a 1.07 μm2 SRAM cell without additional process steps such as local interconnects and shared contacts. We have also used this technology to manufacture a fully-functional SRAM macro and increased its yield by improving the hard mask process for Cu/VLK interconnects and optimizing the gate polypattern. Also, a full, low-k (FLK) interlayer dielectric (SiLK) structure shows superior performance and reliability compared to similar 130 nm structures. v Yoshihiro Takao v Satoshi Nakai v Naoto Horiguchi (Manuscript received December 9, 2002)